Test structure verification of logical BIST: problems and solutions
M. Cogswell, D. Pearl, J. Sage, A. Troidl · 2002
Test Structure Verification (TSV) is the process used to assess the conformance of a circuit to a set of predefine Design For Testability (DFT) rules. Test generation algorithms are typically optimized for circuits that are highly testable, so Test Structure Verification (TSV) ultimately indicates the overall testability of a circuit. Logical BIST (Built In Self Test) is a methodology based on signature analysis which produces patterns used to identify the correctness of the manufactured circuit via specially designed BIST hardware. This paper describes a set of proven production level procedures used to identify and verify the test structure and behavior of BIST hardware. These algorithms are based on the TSV implementation of IBM's TestBench test generation system.