A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter
Hideho Arakida, Masafumi Takahashi, Y. Tsuboi, Takafumi Nishikawa, H. Yamamoto, T. Fujiyoshi, Yoshiyuki Kitasho, Yoshihiro Ueda, Manabu Watanabe, Takeshi Fujita, Toshihiro Terazawa, Kenji Ohmori, M. Koana, Hiroki Nakamura, Eiji Watanabe, Hiroyoshi Ando, T. Aikawa, Tohru Furuyama · 2003
A single-chip MPEG-4 audiovisual LSI in a 0.13 /spl mu/m 5M CMOS technology with 16 Mb embedded DRAM is presented. Four 16 b RISC processors and dedicated hardware accelerators including a 5 GOPS post filtering engine are integrated on the IC. The chip consumes 160 mW at 125 MHz and uses 80 nA in the standby mode. This LSI handles MPEG-4 CIF video encoding at 15 frames/s and audio encoding simultaneously.