An analog systolic neural processing architecture
J.M. Moreno, F. Castillo, Joan Cabestany, Jordi Madrenas, Andrzej Napieralski · IEEE Micro · 1994
Developed for the VLSI implementation of neural network models, our novel analog architecture adds flexibility and adaptability by incorporating digital processing capabilities. Its systolic-based architecture avoids static storage of analog values by transferring the activation values through the chip's processing units. This proposed combination of analog and digital technologies produces a densely packed, high-speed, scalable architecture, designed to easily accommodate learning capabilities.>