A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien Le, Aditya Khargonekar, Pamela Wilcox, John W. Golz, J.B. Kuang, Abraham Mathews, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul Parries, Toshiaki Kirihata, Subramanian S. Iyer · 2008
We present a 1 MB cache subsystem that integrates 2 GHz embedded DRAM macros, charge pump circuits, a 4 Kb one-time-programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5 GB/s peak system data-rate. The eDRAM employs a programmable pipeline, achieving a 1.8 ns latency.