The new memory-efficient hardware architecture of CAVLD in H.264/AVC for mobile system
Sangyoon Park, Kyeong-Yuk Min, Jong‐Wha Chong · 2009
In this paper, we propose a new Context-based Adaptive Variable Decoding (CAVLD) hardware architecture without memory fabrication for mobile process. Previous CAVLD hardware architecture consists of five step blocks and each block gets several bits from controller and Look-Up Tables (LUTs). Many researches on LUTs basically require Read Only Memory (ROM) or Random Access Memory (RAM) fabrication process which is difficult to be implemented in general mobile digital logic fabrication process. In this reason, the hardware architecture for CAVLD inevitably has large hardware area and high power consumption. This paper propose two techniques, which combines five steps into four steps and optimizes LUTs without embedded memory for reducing chip size. By adopting these two techniques, the memory size is reduced 15% and the processing time is reduced 33% compared with previous architectures.