Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation
Guilherme Perin, Daniel Mesquita, Fernando Luís Herrmann, João Baptista Martins · 2010
This paper describes a comparison of two FPGA Montgomery modular multiplication architectures: a fully systolic array and a parallel implementation. The modular multiplication is employed in modular exponentiation processes, which is the most important operation of some public-key cryptographic algorithms and the most popular of them is the RSA encryption scheme. The proposed fully systolic array architecture presents a high-radix implementation with carry propagation between the Processing Elements. The parallel implementation is composed by multipliers blocks in parallel with the Processing Elements and it provides a pipelined operation mode. We compared the time x area efficiency for both architectures as well as a RSA application. The fully systolic array implementation can run the 1024 bit RSA decryption process in just 3.23 ms and the parallel architecture executes the same operation in 6 ms, which means a competitive state-of-art performance for both architectures.