Scalable protocol engine for high-bandwidth communications
Christos J. Georgiou, C.-S. Li · 2002
We have proposed and evaluated a scalable architecture for implementing multi-gigabit protocol engines. The architecture utilizes a combination of custom-made VLSI circuitry and a general-purpose processor, such as the Intel 960 or the IBM PowerPC 403. Time critical operations such as line coding/decoding, CRC generation/checking, context-independent header processing, and buffer management are implemented in the customized VLSI part. These designs are never-the-less scalable and can be cascaded to further increase throughput. Some of the packet level processing, such as context-dependent header processing, are performed by the general-purpose processor. As processing power increases, more and more functions can be included in the general purpose processor. The throughput of this architecture is shown to be adequate for the operations and bit rates currently specified by Fibre Channel. Future CMOS technology advances will have the potential to further improve the raw throughput.