Bit-serial Systolic Array Implementation Of Euclid's Algorithm For Inversion And Division In GF(2/supm)
Jie Guo, Cong-Wei Wang · 2005
This paper presents two serial-in serial-out systolic arrays for inversion or division in GF(2) with the standard basis representation. They can produce results at a rate of one per m cycles after an initial delay of 5m 4 cycles. The proposed arrays involve unidirectional data flow and are highly regular and modular. Thus, they are well suited to VLSI implemenitation with fault-tolerant design. As compared to existing related systolic designs with the same time complexity and I/O format, our proposed arrays gain a significant improvement in hardware area.