Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic
Kenny Johansson, Oscar Gustafsson, Andrew Graham Dempster, Lars Wanhammar · 2004
In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.