Power-efficient heteregoneous parallelism for digital convergence
Kunio Uchiyama · 2008
For embedded systems in the digital-convergence era, various functions such as communication, security, audio, video, and recognition, are required in a single device. However, improving the speed of an embedded LSI in the system is difficult because of the significantly increasing power-consumption problems. Heterogeneous parallelism on an SoC has been studied to solve these problems. A power-thrifty architecture, which combines embedded CPUs and special processing cores such as dynamic reconfigurable processors, has been proposed targeting a superior performance per power ratio and functional flexibility. From the viewpoint of programming, a parallelizing compiler and an Application Program Interface (API) have been developed that are suitable for heterogeneous parallelism. The evaluation results of various applications tested using prototype chips and programs will also be discussed.