Design and implementation of high-performance memory systems for future packet buffers
Jorge García, Jesús Corbal, Llorenç Cerdà, Mateo Valero · 2003
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Building such a high-speed router would raise many technological problems, one of them being the packet buffer design, mainly because in router design it is important to provide worst-case bandwidth guarantees and not just average-case optimizations. A previous