Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models
Mikhail Mikhaylovich Chupilko · 2010
The paper concerns functional testing of hardware models using finite state machines (FSM). Test construction is done by traversing FSM state graph. In this paper we propose a technique for irredundant description of FSM models of parallel-pipeline designs. The technique allows to implicitly specify complex compositional FSM models and to automate construction of test sequences by composing several parallel operations into multi-stimuli.