A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008
This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce thenotationto analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) thecombinationallytestableclass and 2) theacyclicallytestableclass. Then, we introduce a new class oflinear-depthtime-boundedcircuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called thecycle-unrollableRTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.