Synthesis of Sequential Circuits for Robust Path Delay Fault Testability
Sandeep Bhatia, Niraj Kumar Jha · 2005
In this paper, we show how to synthesize sequential circuits for hazard-free robust path delay fault testability using a method called synthesis for parallel scan. Utilizing a new clocking scheme and a previous method for synthesizing completely robustly testable combinational circuits, we first show how complete (i.e. 100%) robust testalsility of sequential circuits can be guaranteed without using enhanced scan, when the number of primary inputs and primary outputs of the sequential circuit is each at least as large as the number of latches. This condition is met by many, but not all, sequential circuits. However, no previous method could guarantee complete robust testability of all path delay faults in a sequential circuit without assuxning complete enhanced scan. When the number of outputs is less (but the number of inputs is more) than the number of latches, we can ensure high, but not necessarily coimplete, robust testability, although for all the benchmarks we considered we did obtain 100% robust testability. For all these methods we only need non-scan, normal latches. The area overheads are relatively small.