High-Throughput FPGA Implementation of 256-bit Montgomery Modular Multiplier
Yaxun Gong, Shuguo Li · 2010
A novel modular multiplier is implemented on FPGA for elliptic curve cryptography (ECC) over GF(p). First, using the embedded 18×18-bit multipliers in the FPGA device, we design a 256-bit Montgomery modular multiplier which spends 3 clock cycles to compute a modular multiplication. Second, the algorithm for Karatusba-Ofman multiplication is used to reduce the number of embedded multipliers needed. Third, to get a higher throughput rate on FPGA devices, we propose a 5-stage pipeline structure to realize the modular multiplier. At last, implemented on Altera Cyclone3 EP3C40F324C6, this modular multiplier runs at the clock rate of 30.38MHz, and performs a 256-bit Montgomery modular multiplication in 0.1¿s, which is much faster than previous implementations on FPGA device.