A versatile and scalable digit-serial/parallel multiplier architecture for finite fields GF(2/sup m/)
Michael J. Hutter, Johann Großschädl, Guy-Armand Kamendje · 2004
We present an architecture for digit-serial multiplication in finite fields GF(2/sup m/) with applications to cryptography. The proposed design uses polynomial basis representation and interleaves multiplication steps with degree reduction steps. An M-bit multiplier works with arbitrary irreducible polynomials and can be used for any binary field of order 2/sup m//spl les/2/sup M/. We introduce a new method for degree reduction which is significantly faster than previously reported iterative techniques. A representative example for a digit-size of d=4, illustrating the reduction circuit, is given. Experimental results show that the proposed method shortens the critical path of the reduction circuit by a factor of between 1.36 and 3.0 for digit-sizes ranging from d=4 to 16.