On fault-tolerant FFT butterfly network design
Shyue-Kung Lu, Cheng‐Wen Wu, Sy‐Yen Kuo · 2002
We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16% and 25% hardware overhead for the bit-level and module-level designs, respectively.