A Symmetric Approach To Single/dual Port (S) RAM On BiCMOS Sea-of-gates
Katsushi Asahina, K. Sawada, M. Ueda, Shinsuke Kayano · 1992
In the development of a RAM macro-cell generator, the most time consuming steps for ASIC vendors are timing verification and layout verification. In this work, symmetrical memory architecture for single-port and dual- port RAM is exhibited. This architecture enables the peripheral circuits of single-port RAM and dual-port RAM identical. It also enables the integration of single-port and dual-port RAM generators into a single generator by holding the leaf-cells commonly. This reduces the time required by timing verification and layout verification. From the experimental result, an 8.011s address access time is obtained from a 512 word x 4 bit dual-part RAM on 0.8pm BiCMOS Sea-Of-Gates.