An 8-b slice GaAs bus logic LSI for a high-speed parallel processing system
Atushi Kameyama, Katsue Kawakyu, Tadahiro Sasaki, T. Seshita, T. Terada, Y. Kitaura, Naotaka Uchitomi, T. Mizoguchi, N. Toyoda, A. Maeda · IEEE Journal of Solid-State Circuits · 1991
An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s.>