Design of High-Speed Floating Point Multiplier
Saroja V. Siddamal, Rajeshwari M. Banakar, B. C. Jinaga · 2008
Floating-point (FP) multiplication finds application in image and signal processing. This paper presents a hardware implementation of optimized IEEE 754 single precision floating-point multiplier. The design is simulated using Modelsim and synthesized using Virtix E Xilinx ISE. An improvement of 57.77% in area and 44.52% in delay is shown.