Real-time integrated video-compression architecture for broadcasting HDTV and multimedia applications
Raja Neogi · 2002
DCT/IDCT based source coding and decoding techniques are widely accepted in HDTV systems and other MPEG based multimedia applications. In this paper we propose a new direct 2-D DCT algorithm based on parallel divide and conquer approach for computation in real-time. The algorithm distributes computation by considering one time-domain coefficient at a time and doing partial computation and updating as every coefficient arrives. A novel parallel and fully pipelined architecture with an effective processing time of one cycle per pixel for an N/spl times/N size block is designed to implement the algorithm. An unique feature of this architecture is that it integrates shuffling and source-coding into a single compact data-path. We avoid the insertion of a FIFO between the motion-estimator and compression engine. The entire block of frequency coefficients are sampled in a single cycle for statistical encoding after compression. Also, we use only N/sup 2/ multipliers and N/sup 2/ adders.