A gated clock scheme for low power scan-based BIST
Yannick Bonhomme, Patrick Girard, L. Guiller, C. Landrault, S. Pravossoudovitch · 2002
Presents a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.