Parallel computation of LFSR signatures
B. Narendran, M. Franklin, Kewal K. Saluja · 2002
Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost a factor of n, where n is the number of processors used. This parallel algorithm is designed by dividing that total number of time-frames to be simulated into partitions, and assigning each partition to a processor. Each processor determines the contribution of its partition to the final signature, and the contributions of different processors are merged, with very little effort, to obtain a single signature. The speedup given by our parallel algorithm is over and above any speedups provided by other sequential speedup techniques such as the use of lookup tables. We also present the results of a simulation study showing the speedup achieved by the parallel algorithm on a Sequent multiprocessor system.>