Architecture and floorplan design techniques for video-rate FIR filters
Rajeev Jain, P.T. Yang, Henry Samueli, T. Yoshino · 2002
Architecture and floorplan design techniques for integrated circuit finite impulse response (FIR) filters that can achieve compact layouts with sample rates in the 25-100-MHz range are described. By exploiting the design techniques described, a functional compiler called FIRGEN that can automate the entire FIR filter design from filter specifications to final chip layout was developed. The use of the transposed form with carry-save addition and CSD multipliers allows sample rates in excess of 100 MHz in 0.8- mu BiCMOS technology, and 70 MHz in 1.2- mu m CMOS. By providing floorplanning constraints for the clock distribution network, the clock skew can be controlled to allow the high sample rate.>