A systolic array architecture for 2-D inverse wavelet transform
J. Singh, A. Antoniou, Dale J. Shpak · 2003
A systolic array architecture for computing the 2-D inverse discrete wavelet transform is proposed. The architecture is derived by performing a thorough data dependence and localization analysis for the 2-D inverse discrete wavelet transform. The design is modular, and can easily be scaled for different levels of wavelet decomposition and filter lengths. The derived architecture for an 8/spl times/8 image has been functionally verified by coding the design in VHDL and simulating it using Mentor Graphics.