Modular Exponentiation on Fine-Grained FPGA
A. A. Tiountchik, Elena Trichina · Symposium on Integrated Circuits and Systems Design · 2000
Taking as a starting point for an FPGA program an efficient bit-level systolic algorithm facilitates the design process but does not automatically guarantee the most efficient hardware solution. We use an example of modular exponentiation with Montgomery multiplication to demonstrate a role of layout optimisation and partitioning in mapping linear systolic arrays onto two-dimensional arrays of FPGA cells.