Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers
Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee · IEEE Design & Test of Computers · 2008
This article discusses a loopback DFT test approach for RFIC chips that provides quick, economical test results at the wafer level. By performing RF testing before chip packaging, the authors reduce test cost. They show that test yield on the ATE for Texas Instruments' RFIC devices is high when this loopback DFT approach is used.