A New Reconfigurable Bit-Serial Systolic Divider for GF(2^m) and GF(p).
Aaron E. Cohen, Keshab K. Parhi · 2006
The paper focuses on the design of a new dual field divider that can achieve performance of 1/m throughput. This dual field division unit can operate at 118 MHz with a latency of 7m-2 cycles and has an area requirement 15 XOR2, 40 AND2, 29 MUX2, and 7 INV gates per processing element with a total of 2m processing elements. It is intended to be used in an elliptic curve crypto-accelerator for GF(2/sup m/) and GF(p). The actual performance for scalar point multiplication in GF(2/sup 571/) running at 100 MHz would be 20.4 kP/s. The actual performance for scalar point multiplication in GF(p) with |p| = 521 running at 100 MHz would be 24.4 kP/s.