On SAT-based Bounded Invariant Checking of Blackbox Designs
Marc Herbstritt, Bernd Becker · Proceedings · 2005
Design verification by property checking is a mandatory task during circuit design. In this context, bounded model checking (BMC) has become popular for falsifying erroneous designs. Additionally, the analysis of partial designs, i.e., circuits that are not fully specified, has recently gained attraction. In this work we analyze how BMC can be applied to such partial designs. Our experiments show that even with the most simple modelling scheme, namely 01X-simulation, a relevant number of errors can be detected. Additionally, we propose a SAT-solver that directly can handle 01X-logic