Design and Implementation of an Efficient Instruction Set for Ternary Processor
Satish S. Narkhede, G. K. Kharate, Bharat S. Chaudhari · International Journal of Computer Applications · 2013
Multi Valued Logic [MVL] is emerging as a promising choice for future computing technology.MVL has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research.The instruction set of the processor is its inherent entity.This paper presents design and implementation of an efficient instruction set for a ternary processor using Very-High-Speed Integrated Circuits, VHSIC Hardware Description Language [VHDL].Twenty one instructions including various addressing modes such as register, direct and immediate mode are designed and implemented for 4-trit ternary processor.The required control signals are appropriately identified in the proposed design and enable the smooth operation of instructions.The designed 4trit instruction set signifies encouraging results that will pave the path for further developments in ternary processors.