A sampling problem from lithography for chip layout
Eric Cator, TJ Dijkema, Michiel E. Hochstenbach, Wouter Mulckhuyse, Mark A. Peletier, Georg Prokert, van der W Weij, D Worm, R.H. Bisseling, K. Dajani, T.J. Dijkema, Leur, van de, J., P.A. Zegeling · TU/e Research Portal · 2007
Given a list with simple polygons and a sampling grid geometry, we calculate the sample (greyscale) value of each grid pixel, such that the residual error in a certain norm is sufficiently small, taking into account that the amount of computational operations should be minimal.