Initial acquisition time of M-ary/SS communication system with several synchronizing chips
Kouji Ohuchi, Hiromasa Habuchi · 2002
M-ary/SS communication systems can improve bit error rate performance under the condition that in which there is an additive white Gaussian noise. Synchronization of M-ary/SS communication systems becomes difficult, however, because M-ary/SS communication systems have several spreading sequences. The authors proposed a simple frame synchronization system which uses one chip in the spreading sequence as the framing signal. This system needs a long time for initial acquisition. The frame synchronization system which makes the initial acquisition time short is proposed. In this system, the number of framing chips (r) is greater than 1. The proposed system corresponds to the conventional system when r=1. As a result, when 10 framing chips are added to a 31 chip spreading sequence under a 10/sup -4/ bit error rate, the initial acquisition time of the proposed system is 88% shorter than that of when 1 chip is added.