An efficient programmable 2-D convolver chip
H.M. Chang, Myung Hoon Sunwoo · 2002
This paper proposes a new real-time 2-D convolution filter architecture to reduce the product of the hardware complexity and propagation delay. To meet the real-time image-processing requirement, several commercial 2-D convolver chips have many parallel multipliers, which occupy a large VLSI area. The implemented chip uses only one special shift-and-accumulator block instead of nine parallel multipliers. Hence the chip can reduce the chip size by more than 50% of existing 2-D convolvers. Moreover, due to a finite state machine, which is controlling input data sequences, the proposed chip does not require row buffers to store three row image data used in the commercial chips. We used the SOG cell library (KG60K). The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, i.e., the standard of ITU-R BT.601.