A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs
Enrique Cantó, J.M. Moreno, Joan Cabestany, I. Lacadena, J. M. Insenser · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2001
This paper will describe a systematic method to map synchronous digital systems into dynamically reconfigurable programmable logic (i.e., programmable logic able to swap in real time the configuration defining the functionality of the system). The method is based on a temporal bipartitioning technique that is able to separate the static implementation of a circuit in two temporal independence hardware contexts. As the experimental results show, the method is capable of improving the functional density of the dynamic implementation with respect to the static one.