An intelligent subprocessor for hardware emulation with 20-MOPS performance
Hiroshi Nakamura, T. Sawase, Y. Akao, S. Masumura, Masanao Hayashi, H. Ohsuga, Y. Satoh, T. Aizawa · IEEE Journal of Solid-State Circuits · 1991
An intelligent subprocessor (ISP) for hardware emulation of embedded controller subsystems is proposed. The subprocessor achieves 20 MOPS and 50-ns resolution of task switching for 12 tasks. It introduces task switching based on a time-slot assignment mechanism, one-clock-per-instruction (CPI) architecture, and parallel processing of a plurality of operations in a single-instruction execution. It also introduces field-programmable internal EPROMs with self-detecting power saving circuits. This subprocessor can emulate simple hardware functions such as timers and serial interfaces, as well as complex hardware functions such as DC motor controllers. A test chip with 90 K transistors was fabricated on a 4.12-mm*4.98-mm area by using 1.3- mu m CMOS technology.>