Matched filter implementation on FPGA for integrand code using a real-valued shift-orthogonal finite-lenght sequence
Takahiro Matsumoto, Shinya Matsufuji · International Conference on Advanced Communication Technology · 2009
In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp a periodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters is implemented ona field programmable gate array (FPGA) corresponding to 400,000 gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.