Sequential circuit diagnosis based on formal verification techniques
Gianpiero Cabodi, Paolo Enrico Camurati, Fulvio Corno, P. Prinetto, Matteo Sonza Reorda · 2005
This paper‘ deals with the generation of diagnostic test sequences for real-size synchronous sequential circuits. A modified fault simulator is used for assessing the diagnostic power of existing detection-oriented test patterns and a diagnostic procedure for generating new ones is described. The diagnostic procedure successfully exploits symbolic FSM equivalence proof algorithms. In order to resort to product machine traversal only when really needed, special checks are perfo:rrned to verify combinational identity and identity on rt:achable states. As all faults are attributed to their equivalence class, this method may be used to build a complete and exact diagnostic tree. Experimental results on ISCAS’89 circuits show the feasibility of the’ approach ’.