Fault modeling for physical failures for CMOS circuits
Mona Elwakkad Zaghloul, Desa Gobovic · 2003
The authors propose a fault simulation model for CMOS VLSI circuits which can handle physical faults as gate-to-drain/source shorts. A relation is established between the inverse voltage of a fault-free inverter and the faulty output voltage of a faulty inverter. This relation is then used to study the propagation of the faulty signal through a successive gate.>