Rate-optimal DSP synthesis by pipeline and minimum unfolding
Lih‐Gwo Jeng, Liang‐Gee Chen · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1994
This paper presents a rate-optimal scheduling for real-time DSP algorithms. By using pipelining and unfolding techniques, the parallel characteristics of recursive DSP algorithms can be exploited. A novel unfolding technique is developed to unravel all concurrency in the recursive data flow graph. A perfect rate unfolded data flow graph is also introduced, which can cause a fully static rate optimal functional pipeline schedule. Experimental results have shown that the proposed method can always yield rate-optimal designs with a smaller unfolding factor compared to previous studies.>