A modified MAP decoder architecture for low power consumption using folded technique
S. Shiyamala, V. Rajamani · International Journal of Electronics · 2012
A modified MAP decoder architecture to reduce the power using folded technique is presented in this article. Firstly, the folded technique is applied in the interleaving and deinterleaving unit and then in the MAP decoder unit. The number of latches is reduced by using folded technique in the interleaving and deinterleaving unit. Here the end-to-end delay by using the proposed folded technique in the interleaving block is 2 M. But existing reports reveal that end-to-end delay is 2MN − 2 M + 2 for BI and M(N − 1) for FCI. In addition to the end-to-end delay, the number of latches is also reduced by using folded technique. We have used only M − 2 latches, whereas for other methods the number of latches utilised is more. The proposed MAP decoder reduce the memory elements up to 88% for the block interleaver, when M = NJ. In addition to that we achieved a memory element of 2 K −1 + 4 when calculating LLR by applying folded technique in the MAP decoder. Total power consumption is 160.3mW when folded technique is used in the interleaving block and the MAP decoder section. This ratio is less than the existing reported values for K = 5, code rate ½ and k = 4.