An Integrated Functional Verification Tool for FPGA Systems
Trong‐Yen Lee, Yang‐Hsin Fan, Shih-Chin Yen, Chia‐Chun Tsai, Rong-Shue Hsiao · 2007
Hundreds of thousands circuits can not be verified easily while develop a field programmable gate array (FPGA) system. In this paper, we develop a functional verification tool, namely FVT, to verify the designer defined specification of functionalities with simulator and emulator in a FPGA system. In addition, FVT can point out the exact bugs for functionality where locates at specific cycle. Experiment results show that FVT can save time up to 99%.