A New Method for Generating Tests for Delay Faults in Non-Scan Circuits
Rahul Agrawal, Vishwani D. Agrawal · 2005
A new method is developed for generating tests for path delay faults in synchronous sequential circuits using any available sequential circuit test generation program. All paths through the combinational logic are searched and two potential faults for each path, corresponding to the propagation of rising and falling signals at the source of the path, are considered. To generate a test sequence for a path delay fault, we augment the netlist model of the circuit under test with a logic block such that the testing for a certain single stuck type fault in this block is equivalent to the testing of the path delay fault. The added logic consists of a pair of flip-flops and a few combinational gates that are driven by the signals feeding the gates on the path. A stuck-at-1 fault in this logic is activated and its effect is latched into the destination flip-flop of the path only when all signals along the path are set in the states required for the delay test. The fault efSect is then propagated to a primary output. The test sequence for the stuck fault, thus performs all three functions, namely, initialization, path activation and fault propagation, required for the testing of the delay fault. We use a sequential circuit test generator to obtain a test sequence for this stuck type of fault. A hazard avoidance procedure to produce robust tests, although not fully implemented in our prototype test generator, is given. Experimental results on sequential benchmark circuits show the practicality of this method for general nonscan as well as for scan and scanlhold type of circuits.