On Test Generation With Test Vector Improvement
Irith Pomeranz, Sudhakar M. Reddy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2010
We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cubetis generated at an arbitrary iteration of the test generation process, the test vector improvement step modifiestso as to increase the number of yet-undetected target faults thattdetects. This is done in this paper using a simulation-based process. We show that even iftwas generated using dynamic test compaction heuristics, it is possible to improvetfurther. Whentis partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits oft. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults).