Hardware-assisted scalable flow control of shared receive queue
Teruo Tanimoto, Takatsugu Ono, Kohta Nakashima, Takashi Miyoshi · 2014
The total number of processor cores in supercomputers is increasing while memory size per core is decreasing due to the adoption of processors with multiple cores. Shared Receive Queue is a technique that effectively reduces the memory usage of buffers, but the absence of flow control results in excess buffer pools. We propose a hardware-assisted flow control that reduces flow control latency by 95.1%, thus enabling scalable supercomputers with multi-core processors.