A power-saving 1Gbps Irregular LDPC Decoder based on high-efficiency messagepassing
Wenming Tang, Wen Ji, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2008
In this paper we proposed a partially-parallel decoder for irregular LDPC codes from IEEE802.11n standards. Our proposed decoder adopts high-efficiency message-passing algorithm and uses the min-sum algorithm handle the message-passing to reduce the hardware implementation complexity and area, and keep high throughput. Considering reducing the power consumption, we used half-registers and half-memory to store the temporary intrinsic messages. The wasted motion of shift- register was suppressed.�H This strategy would save us higher as 30% power under good channel condition. The synthesis result in TSMC 0.18um COMS technology demonstrated that for (1296,324) irregular LDPC code achieved high throughput (1.05Gbps) at the frequency of 200MHz, with 6% area reduction.