Test application time reduction for scan circuits using limited scan operations
Cho yonsang, Irith Pomeranz, Sudhakar M. Reddy · 2004
We describe a static compaction procedure for full-scan circuits. The procedure accepts a (compact) test set generated for the combinational logic of the circuit and produces a test set with reduced test application time and tester memory, requirements. The reductions are achieved by combining pairs of tests. When a pair of tests is combined, the scan operation required between the two tests is replaced with a limited scan operation. Under a limited scan operation a scan chain of length L is shifted a number of positions S /spl les/ L. As a special case, S = 0 implies that the scan operation between two tests is eliminated altogether. We introduce several techniques to ensure that consideration of test pairs can be done efficiently and results in very high levels of test compaction for benchmark circuits.