Power and performance optimization at the system level
Valentina Salapura, R. Bickford, Matthias A. Blumrich, A. A. Bright, Dong Chen, P. Coteus, Alan Gara, Mark Giampapa, Michael K. Gschwind, Manish Gupta, Shawn A. Hall, Ruud A. Haring, Philip Heidelberger, D. Hoenicke, Gerard V. Kopcsay, Martin Ohmacht, Rick A. Rand, Todd Takken, Pavlos M. Vranas · 2005
The BlueGene/L supercomputer has been designed with a focus on power/performance efficiency to achieve high application performance under the thermal constraints of common data centers. To achieve this goal, emphasis was put on system solutions to engineer a power-efficient system. To exploit thread level parallelism, the BlueGene/L system can scale to 64 racks with a total of 65536 computer nodes consisting of a single compute ASIC integrating all system functions with two industry-standard PowerPC microprocessor cores in a chip multiprocessor configuration. Each PowerPC processor exploits data-level parallelism with a highperformance SIMD floating point unit. To support good application scaling...