A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs
M. Renovell, M. Ildevert, Y. Bertrand · 2005
Many BIST schemes exist for large PLAs, nevertheless they are two unsolved problems. The first point concerns the basic fault models: it has been demonstrated that the classical fault models used for nMOS and pseudo-nMOS PLAs are inadequate for dynamic CMOS PLAs [ 11. The second point concerns the unacceptable required additional area [2]. The authors have previously defined new, realistic and adequate fault models [l]. From these new fault models, a new BIST design for dynamic CMOS PLA is proposed which is based on circuit partitioning, easy universal test sequence generation and original parallel output response compression. The resulting implementation requires a very low area overhead.