High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier
S. S. Nayak, Pramod Kumar Meher · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1999
In this paper, we propose a fully pipelined two-dimensional (2-D) bit level systolic architecture for efficient implementation of discrete orthogonal transforms using a serial-parallel vector-matrix multiplication scheme based on the Baugh-Wooley algorithm. Apart from its regularity and simplicity, the proposed structure yields high throughput due to massive parallelism across the 2-D mesh. The area- and time-complexities of the proposed structure are (ON/sup 2/) and O(2nN/sup 2/), respectively, for implementation of N-point transform, where n is the wordlength.