Generating VHDL-AMS Models of Digital-to-Analogue Converters From MATLAB®/SIMULINK®
Alexandre César Rodrigues da Silva, Ian Andrew Grout, Jeffrey M. Ryan, Thomas O'Shea · 2007
Today, the trend within the electronics industry is for the use of rapid and advanced simulation methodologies in association with synthesis toolsets. This paper presents an approach developed to support mixed-signal circuit design and analysis. The methodology proposed shows a novel approach to the problem of developing behavioral model descriptions of mixed-signal circuit topologies, by construction of a set of subsystems, that supports the automated mapping of MATLABreg/SIMULINKregmodels to structural VHDL-AMS descriptions. The tool developed, named MS2SV, reads a SIMULINKregmodel file and translates it to a structural VHDL-AMS code. It also creates the file structure required to simulate the translated model in the SystemVisiontrade. To validate the methodology and the developed program, the DAC08, AD7524 and AD5450 data converters were studied and initially modelled in MATLABreg/SIMULINKreg. The VHDL-AMS code generated automatically by MS2SV, (MATLABreg/SIMULINKregto SystemVisiontrade), was then simulated in the SystemVisiontrade. The simulation results show that the proposed approach, which is based on VHDL-AMS descriptions of the original model library elements, allows for the behavioural level simulation of complex mixed-signal circuits.